Cardiovascular diseases are a major threat to the survival of human beings. An electrocardiogram is used in the diagnosis of heart diseases. But many types of noises are present to deter the quality of ECG signals. Thus, these noises must be filtered using a Digital filter like FIR (Finite Impulse Response) filter. There are different approaches to designing an FIR filter. One of the prominent ways is by using windows. There are other ways of designing the FIR filters but filtering using windows is one of the fastest ways of designing the FIR filters. In this paper different orders to filter has been analyzed and the best order to filter the ECG is found. Using that order different windows of FIR filter has been designed using Xilinx System Generator which is used to filter the noisy ECG signal. Also, various windows have been compared for filtering noises in ECG like Baseline Wander noise and Muscle Artifacts noise. The best window among all the windows is found out using MATLAB Simulink.

The present trend of low power and area has led to the design of many efficient algorithms for speech processing in portable devices.  In biomedical applications like hearing aid, high performance is not the key area of interest. Area and power also play a major role. There are many factors that affect market penetration. So, the system can run as slow as possible to trade speed for power and area. An area-efficient folded IIR filter is designed. The folded architecture uses the concept of time multiplexing and it has only one multiplier and one adder to perform all the operations. Thus, the area is reduced, and this filter is converted into an IP. The area and resource utilization of the folded IIR filter is compared with the normal IIR filter design. AFIR filter is also designed and converted into an IP. This FIR IP is used in the block design to process a corrupted audio signal. Zed board is a part of Xilinx zynq -7000 All Programmable SoC. It consists of a processing system and programming logic. The filter design is implemented in the programming logic part. The design is synthesized and the bitstream is generated. The generated bitstream along with the hardware is exported to SDK where the corrupted audio signal is processed on zed board.

This paper proposes a new method for rejecting the Continuous Wave Interferences (CWI) in the Global Positioning System (GPS) receivers. The proposed filter is made by cascading an adaptive Finite Impulse Response (FIR) filter and a Wavelet Packet Transform (WPT) based filter. Although adaptive FIR filters are easy to implement and have a linear phase, they create self-noise in the rejection of strong interferences.Moreover, the WPT which provides detailed signal decomposition can be used for the excision of single-tone and multi-tone CWI and also for de-noising the retrieved GPS signal. By cascading these two filters, the self-noise imposed by FIR filter and the remaining jamming effects on GPS signal can be eliminated by the WPT based filter. The performance analysis of the proposed cascade filter is presented in this paper and it is compared with the FIR and the WPT based filters. Experimental results illustrate that the proposed method offers a better performance under the interference environments of interest in terms of the signal-to-noise ratio gain and mean square error factors compared to previous methods.

This paper introduces a method of designing an M-channel, causal, stable and perfect reconstruction (PR), infinite impulse response (IIR), parallel uniform discrete Fourier transform (DFT) filter banks. The basic idea behind this is based on an efficient technique of designing and implementing narrowband lowpass finite impulse response (FIR) filters, called the interpolated FIR (IFIR) technique. In this paper, we have extended the IFIR concept to the IIR filter, known as Interpolated IIR (IIIR), and applied the concept to IIR DFT filter banks. It has been shown that this technique is good for IIR DFT filter banks in polyphase oversampled case and also has a modular structure which is therefore very useful for very large scale integration (VLSI) implementation.